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High Performance ISM Band Transceiver IC ADF7025
FEATURES
Low power, zero-IF RF transceiver Frequency bands 431 MHz to 464 MHz 862 MHz to 870 MHz 902 MHz to 928 MHz Data rates supported 9.6 kbps to 384 kbps, FSK 2.3 V to 3.6 V power supply Programmable output power -16 dBm to +13 dBm in 63 steps Receiver sensitivity -104.2 dBm at 38.4 kbps, FSK -100 dBm at 172.8 kbps, FSK -95.8 dBm at 384 kbps, FSK Low power consumption 19 mA in receive mode 28 mA in transmit mode (10 dBm output) On-chip VCO and Fractional-N PLL On-chip, 7-bit ADC and temperature sensor Digital RSSI Integrated TRx switch Leakage current < 1 A in power-down mode
APPLICATIONS
Wireless audio/video Remote control/security systems Wireless metering Keyless entry Home automation
FUNCTIONAL BLOCK DIAGRAM
RSET CREG(1:4) ADCIN MUXOUT
RLNA
BIAS
LDO(1:4)
OFFSET CORRECTION
TEMP SENSOR
TEST MUX
LNA RFIN RFINB GAIN OFFSET CORRECTION LP FILTER RSSI MUX 7-BIT ADC
FSK DEMODULATOR
DATA SYNCHRONIZER
CE AGC CONTROL
- MODULATOR
DATA CLK Tx/Rx CONTROL DATA I/O
FSK MOD CONTROL
INT/LOCK DIVIDERS/ MUXING
RFOUT
DIV P
N/N+1 SLE SERIAL PORT SDATA SREAD SCLK DIV R RING OSC CLK DIV
05542-001
VCO CP PFD
VCOIN CPOUT
OSC1
OSC2
CLKOUT
Figure 1.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2006 Analog Devices, Inc. All rights reserved.
ADF7025 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 General Description ......................................................................... 3 Specifications..................................................................................... 4 Timing Characteristics..................................................................... 7 Timing Diagrams.......................................................................... 7 Absolute Maximum Ratings............................................................ 9 ESD Caution.................................................................................. 9 Pin Configuration and Function Descriptions........................... 10 Typical Performance Characteristics ........................................... 12 Frequency Synthesizer ................................................................... 15 Reference Input Section............................................................. 15 Choosing Channels for Best System Performance................. 17 Transmitter ...................................................................................... 18 RF Output Stage.......................................................................... 18 Modulation Scheme ................................................................... 18 Receiver............................................................................................ 19 RF Front End............................................................................... 19 RSSI/AGC.................................................................................... 20 FSK Demodulators on the ADF7025....................................... 20 FSK Correlator/Demodulator................................................... 20 Linear FSK Demodulator .......................................................... 22 Automatic Sync Word Recognition ......................................... 22 Applications Section....................................................................... 23 LNA/PA Matching...................................................................... 23 Transmit Protocol and Coding Considerations ..................... 24 Device Programming after Initial Power-Up ............................. 24 Interfacing to Microcontroller/DSP ........................................ 24 Serial Interface ................................................................................ 27 Readback Format........................................................................ 27 Registers........................................................................................... 28 Register 0--N Register............................................................... 28 Register 1--Oscillator/Filter Register...................................... 29 Register 2--Transmit Modulation Register ............................ 30 Register 3--Receiver Clock Register ....................................... 31 Register 4--Demodulator Setup Register ............................... 32 Register 5--Sync Byte Register................................................. 33 Register 6--Correlator/Demodulator Register ...................... 34 Register 7--Readback Setup Register...................................... 35 Register 8--Power-Down Test Register .................................. 36 Register 9--AGC Register......................................................... 37 Register 10--AGC 2 Register.................................................... 38 Register 12--Test Register......................................................... 39 Register 13--Offset Removal and Signal Gain Register ....... 40 Outline Dimensions ....................................................................... 41 Ordering Guide .......................................................................... 41
REVISION HISTORY
2/06--Rev. 0 to Rev. A Replaced Figure 40 ................................................................ Page 29 1/06--Revision 0: Initial Version
Rev. A | Page 2 of 44
ADF7025 GENERAL DESCRIPTION
The ADF7025 is a low power, highly integrated FSK transceiver. It is designed for operation in the license-free ISM bands of 433 MHz, 863 MHz to 870 MHz, and 902 MHz to 928 MHz. The ADF7025 can be used for applications operating under the European ETSI EN300-220 or the North American FCC (Part 15) regulatory standards. The ADF7025 is intended for wideband, high data rate applications with deviation frequencies from 100 kHz to 750 kHz and data rates from 9.6 kbps to 384 kbps. A complete transceiver can be built using a small number of external discrete components, making the ADF7025 very suitable for price-sensitive and area-sensitive applications. The transmit section contains a VCO and low noise Fractional-N PLL with output resolution of <1 ppm. The VCO operates at twice the fundamental frequency to reduce spurious emissions and frequency pulling problems. The transmitter output power is programmable in 0.3 dB steps from -16 dBm to +13 dBm. The transceiver RF frequency, channel spacing, and modulation are programmable using a simple 3-wire interface. The device operates with a power supply range of 2.3 V to 3.6 V and can be powered down when not in use. A zero-IF architecture is used in the receiver, minimizing power consumption and the external component count, while avoiding the need for image rejection. The baseband filter (low-pass) has programmable bandwidths of 300 kHz, 450 kHz, and 600 kHz. A high-pass pole at ~60 kHz eliminates the problem of dc offsets that is characteristic of zero-IF architecture. The ADF7025 supports a wide variety of programmable features, including Rx linearity, sensitivity, and filter bandwidth, allowing the user to trade off receiver sensitivity and selectivity against current consumption, depending on the application. An on-chip ADC provides readback of an integrated temperature sensor, an external analog input, the battery voltage, or the RSSI signal, which provides savings on an ADC in some applications. The temperature sensor is accurate to 10C over the full operating temperature range of -40C to +85C. This accuracy can be improved by doing a 1-point calibration at room temperature and storing the result in memory.
Rev. A | Page 3 of 44
ADF7025 SPECIFICATIONS
VDD = 2.3 V to 3.6 V, GND = 0 V, TA = TMIN to TMAX, unless otherwise noted. Typical specifications are at VDD = 3 V, TA = 25C. All measurements are performed using the EVAL-ADF7025DB1 using PN9 data sequence, unless otherwise noted. Table 1.
Parameter RF CHARACTERISTICS Frequency Ranges (Direct Output) Frequency Ranges (Divide-by-2 Mode) Phase Frequency Detector Frequency TRANSMISSION PARAMETERS Data Rate FSK FSK Frequency Deviation Min 862 902 431 RF/256 Typ Max 870 928 464 24 Unit MHz MHz MHz Test Conditions VCO adjust = 0, VCO bias = 10 VCO adjust = 3, VCO bias = 12 See conditions for direct output
Deviation Frequency Resolution Gaussian Filter BT Transmit Power1 Transmit Power Variation vs. Temperature Transmit Power Variation vs. VDD Transmit Power Flatness Programmable Step Size -20 dBm to +13 dBm Spurious Emissions Integer Boundary Reference Harmonics Second Harmonic Third Harmonic All Other Harmonics VCO Frequency Pulling Optimum PA Load Impedance
9.6 100 100 100 221 0.5 -20 1 1 1 0.3125 -55 -65 -27 -21 -35 30 39 + j61 48 + j54 54 + j94
384 311.89 748.54 374.27
kbps kHz kHz kHz Hz dBm dB dB dB dB dBc dBc dBc dBc dBc kHz rms
PFD = 10 MHz, direct output PFD = 24 MHz, direct output PFD =24MHz, divide-by-2 mode PFD = 3.625 MHz VDD = 3.0 V, TA = 25C From -40C to +85C From 2.3 V to 3.6 V at 915 MHz, TA = 25C From 902 MHz to 928 MHz, 3 V, TA = 25C
+13
50 kHz loop B/W
Unfiltered conductive
DR = 9.6 kbps FRF = 915 MHz FRF = 868 MHz FRF = 433 MHz At BER = 1E - 3, FRF = 915 MHz, LNA and PA matched separately2 FDEV = 200 kHz, LPF B/W = 300kHz FDEV = 200 kHz, LPF B/W = 450kHz FDEV = 450kHz, LPF B/W = 600kHz Programmable
RECEIVER PARAMETERS FSK Input Sensitivity Sensitivity at 38.4 kbps Sensitivity at 172.8 kbps Sensitivity at 384 kbps Baseband Filter (Low-Pass) Bandwidths -104.2 -100 -95.8 300 450 600 LNA and Mixer, Input IP3 Enhanced Linearity Mode Low Current Mode High Sensitivity Mode Rx Spurious Emissions3 +6.8 -3.2 -35 -57 -47 dBm dBm dBm kHz kHz kHz dBm dBm dBm dBm dBm
Pin = -20 dBm, 2 CW interferers FRF = 915 MHz, f1 = FRF + 3 MHz F2 = FRF + 6 MHz, maximum gain <1 GHz at antenna input >1 GHz at antenna input
Rev. A | Page 4 of 44
ADF7025
Parameter CHANNEL FILTERING Adjacent Channel Rejection (Offset = 1 x LP Filter BW Setting) Second Adjacent Channel Rejection (Offset = 2 x LP Filter BW Setting) Third Adjacent Channel Rejection (Offset = 3 x LP Filter BW Setting) Co-Channel Rejection Wideband Interference Rejection BLOCKING 1 MHz 2 MHz 10 MHz Saturation (Maximum Input Level) LNA Input Impedance Min Typ 27 40 43 -2 70 +24 Max Unit dB dB dB dB dB Maximum rejection measured with CW interferer at center of channel Swept from 100 MHz to 2 GHz, measured as channel rejection Desired signal (38.4 kbps DR, 200 kHz FDEV, 300 KHz LP filter B/W) 6 dB above the input sensitivity level, CW interferer power level increased until BER = 10-3 FSK mode, BER = 10-3 FRF = 915 MHz, RFIN to GND FRF = 868 MHz FRF = 433 MHz Test Conditions Desired signal (38.4 kbps DR, 200 kHz FDEV, 300 KHz LP filter B/W) 6 dB above the input sensitivity level, CW interferer power level increased until BER = 10-3
42 51 64 12 24 - j60 26 - j63 71 - j128 -100 to -36 2 3 150 65 83
dB dB dB dBm dBm dB dB s MHz/V MHz/V dBc/Hz dBc/Hz Hz s
RSSI Range at Input Linearity Absolute Accuracy Response Time PHASE-LOCKED LOOP VCO Gain
Phase Noise (In-Band) Phase Noise (Out-of-Band) Residual FM PLL Settling Time
-89 -110 128 40
902 MHz to 928 MHz band, VCO adjust = 3, VCO_BIAS_SETTING = 12 862 MHz to 870 MHz band, VCO adjust = 0, VCO_BIAS_SETTING = 10 PA = 0 dBm, VDD = 3.0 V, PFD = 10 MHz, FRF = 868 MHz, VCO_BIAS_SETTING = 10 1 MHz offset From 200 Hz to 20 kHz, FRF = 868MHz Measured for a 10 MHz frequency step to within 5 ppm accuracy, PFD = 20 MHz, LBW = 50kHz
REFERENCE INPUT Crystal Reference External Oscillator Load Capacitance Crystal Start-Up Time Input Level TIMING INFORMATION Chip Enabled to Regulator Ready Crystal Oscillator Startup Time Tx to Rx Turnaround Time
3.625 3.625 33 1.0
24 24
MHz MHz pF ms CMOS levels s ms
Using 33 pF load capacitors
10 1 150 s + (5 x TBIT)
CREG = 100 nF With 19.2 MHz XTAL Time to synchronized data, includes AGC settling
Rev. A | Page 5 of 44
ADF7025
Parameter LOGIC INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IINH/IINL Input Capacitance, CIN Control Clock Input LOGIC OUTPUTS Output High Voltage, VOH Output Low Voltage, VOL CLKOUT Rise/Fall CLKOUT Load TEMPERATURE RANGE, TA POWER SUPPLIES Voltage Supply VDD Transmit Current Consumption -20 dBm -10 dBm 0 dBm 10 dBm Receive Current Consumption Low Current Mode High Sensitivity Mode Power-Down Mode Low Power Sleep Mode
1 2 3
Min 0.7 x VDD
Typ
Max
Unit V V A pF MHz V V ns pF C
Test Conditions
0.2 x VDD 1 10 50 DVDD - 0.4 0.4 5 10 +85
IOH = 500 A IOL = 500 A
-40
2.3
3.6
V
All VDD pins must be tied together FRF = 915 MHz, VDD = 3.0 V, PA is matched in to 50
14.6 15.8 19.3 28 19 21 0.1 1
mA mA mA mA mA mA A
Measured as maximum unmodulated power. Output power varies with both supply and temperature. Sensitivity for combined matching network case is typically 2 dB less than separate matching networks. Follow the matching and layout guidelines in the LNA/PA Matching section to achieve the relevant FCC/ETSI specifications.
Rev. A | Page 6 of 44
ADF7025 TIMING CHARACTERISTICS
VDD = 3 V 10%; VGND = 0 V, TA = 25C, unless otherwise noted. Table 2.
Parameter1 t1 t2 t3 t4 t5 t6 t8 t9 t10
1
Limit at TMIN to TMAX <10 <10 <25 <25 <10 <20 <25 <25 <10
Unit ns ns ns ns ns ns ns ns ns
Test Conditions/Comments SDATA to SCLK setup time SDATA to SCLK hold time SCLK high duration SCLK low duration SCLK to SLE setup time SLE pulse width SCLK to SREAD data valid, readback SREAD hold time after SCLK, readback SCLK to SLE disable time, readback
Guaranteed by design, not production tested.
TIMING DIAGRAMS
t3
SCLK
t4
t1
t2
DB1 (CONTROL BIT C2) DB0 (LSB) (CONTROL BIT C1)
SDATA
DB31 (MSB)
DB30
DB2
t6
SLE
t5
Figure 2. Serial Interface Timing Diagram
t1
SCLK
t2
SDATA REG7 DB0 (CONTROL BIT C1) SLE
t3
t10
X RV16 RV15 RV2 RV1
05542-003
SREAD
t8
t9
Figure 3. Readback Timing Diagram
Rev. A | Page 7 of 44
05542-002
ADF7025
1 x DATA RATE/32 RxCLK 1/DATA RATE
Figure 4. RxData/RxCLK Timing Diagram
Rev. A | Page 8 of 44
05542-004
RxDATA
DATA
ADF7025 ABSOLUTE MAXIMUM RATINGS
TA = 25C, unless otherwise noted. Table 3.
Parameter VDD to GND1 Analog I/O Voltage to GND Digital I/O Voltage to GND Operating Temperature Range Industrial (B Version) Storage Temperature Range Maximum Junction Temperature MLF JA Thermal Impedance Lead Temperature Soldering Vapor Phase (60 sec) Infrared (15 sec)
1
Rating -0.3 V to +5 V -0.3 V to AVDD + 0.3 V -0.3 V to DVDD + 0.3 V -40C to +85C -65C to +125C 125C 26C/W 235C 240C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. This device is a high performance, RF integrated circuit with an ESD rating of <2 kV, and it is ESD sensitive. Proper precautions should be taken for handling and assembly.
GND = CPGND = RFGND = DGND = AGND = 0 V.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. A | Page 9 of 44
ADF7025 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
45 VCO GND 42 CPOUT 48 CVCO 47 GND1 41 VREG3 46 GND 44 GND 43 VDD 39 OSC1 40 VDD3 38 OSC2 37 MUXOUT
VCOIN VREG1 VDD1 RFGND RFIN RFINB VDD4
1 2 3 5 6 7 9
PIN 1 INDICATOR
36 CLKOUT 35 DATA CLK 34 DATA I/O 33 INT/LOCK 32 VDD2 31 VREG2 30 ADCIN 29 GND2 28 SCLK 27 SREAD 26 SDATA 25 SLE
RFOUT 4
ADF7025
TOP VIEW (Not to Scale)
R LNA 8 RSET 10 VREG4 11 GND4 12
MIX_Q 15 MIX_Q 16 FILT_I 18 GND4 19 TEST_A 23 MIX_I 13 FILT_I 17 FILT_Q 20 FILT_Q 21 MIX_I 14 GND4 22 CE 24
Figure 5. Pin Configuration
Table 4. Pin Function Descriptions
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 to 18 19, 22 20, 21, 23 24 25 26 27 28 Mnemonic VCOIN VREG1 VDD1 RFOUT RFGND RFIN RFINB RLNA VDD4 RSET VREG4 GND4 MIX/FILT GND4 FILT/TEST_A CE SLE SDATA SREAD SCLK Description The tuning voltage on this pin determines the output frequency of the voltage-controlled oscillator (VCO). The higher the tuning voltage, the higher the output frequency. Regulator Voltage for PA Block. A 100 nF in parallel with a 5.1 pF capacitor should be placed between this pin and ground for regulator stability and noise rejection. Voltage Supply for PA Block. Decoupling capacitors of 0.1 F and 10 pF should be placed as close as possible to this pin. All VDD pins should be tied together. The modulated signal is available at this pin. Output power levels are from -20 dBm to +13 dBm. The output should be impedance-matched to the desired load using suitable components. See the Transmitter section. Ground for Output Stage of Transmitter. LNA Input for Receiver Section. Input matching is required between the antenna and the differential LNA input to ensure maximum power transfer. See the LNA/PA Matching section. Complementary LNA Input. See the LNA/PA Matching section. External bias resistor for LNA. Optimum resistor is 1.1 k with 5% tolerance. Voltage supply for LNA/MIXER Block. This pin should be decoupled to ground with a 10 nF capacitor. External Resistor to Set Charge Pump Current and Some Internal Bias Currents. Use 3.6 k with 5% tolerance. Regulator Voltage for LNA/MIXER Block. A 100 nF capacitor should be placed between this pin and GND for regulator stability and noise rejection. Ground for LNA/MIXER Block. Signal Chain Test Pins. These pins are high impedance under normal conditions and should be left unconnected. Ground for LNA/MIXER Block. Signal Chain Test Pins. These pins are high impedance under normal conditions and should be left unconnected. Chip Enable. Bringing CE low puts the ADF7025 into complete power-down. Register values are lost when CE is low, and the part must be reprogrammed once CE is brought high. Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one of the four latches. A latch is selected using the control bits. Serial Data Input. The serial data is loaded MSB first with the two LSBs as the control bits. This pin is a high impedance CMOS input. Serial Data Output. This pin is used to feed readback data from the ADF7025 to the microcontroller. The SCLK input is used to clock each readback bit (ADC readback) from the SREAD pin. Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched into the 24-bit shift register on the CLK rising edge. This pin is a digital CMOS input.
Rev. A | Page 10 of 44
05542-006
ADF7025
Pin No. 29 30 31 32 33 Mnemonic GND2 ADCIN VREG2 VDD2 INT/LOCK Description Ground for Digital Section. Analog-to-Digital Converter Input. The internal 7-bit ADC can be accessed through this pin. Full scale is 0 V to 1.9 V. Readback is made using the SREAD pin. Regulator Voltage for Digital Block. A 100 nF in parallel with a 5.1 pF capacitor should be placed between this pin and ground for regulator stability and noise rejection. Voltage Supply for Digital Block. A decoupling capacitor of 10 nF should be placed as close as possible to this pin. Bidirectional Pin. In output mode (interrupt mode), the ADF7025 asserts the INT/LOCK pin when it has found a match for the preamble sequence. In input mode (lock mode), the microcontroller can be used to lock the demodulator threshold when a valid preamble has been detected. Once the threshold is locked, NRZ data can be reliably received. In this mode, a demodulator lock can be asserted with minimum delay. Transmit Data Input/Received Data Output. This is a digital pin, and normal CMOS levels apply. In receive mode, the pin outputs the synchronized data clock. The positive clock edge is matched to the center of the received data. A Divided-Down Version of the Crystal Reference with Output Driver. The digital clock output can be used to drive several other CMOS inputs, such as a microcontroller clock. The output has a 50:50 mark-space ratio. This pin provides the lock_detect signal, which is used to determine if the PLL is locked to the correct frequency. Other signals include regulator_ready, which is an indicator of the status of the serial interface regulator. The reference crystal should be connected between this pin and OSC1. A TCXO reference can be used by driving this pin with CMOS levels and disabling the crystal oscillator. The reference crystal should be connected between this pin and OSC2. Voltage Supply for the Charge Pump and PLL Dividers. This pin should be decoupled to ground with a 0.01 F capacitor. Regulator Voltage for Charge Pump and PLL Dividers. A 100 nF in parallel with a 5.1 pF capacitor should be placed between this pin and ground for regulator stability and noise rejection. Charge Pump Output. This output generates current pulses that are integrated in the loop filter. The integrated current changes the control voltage on the input to the VCO. Voltage Supply for VCO Tank Circuit. This pin should be decoupled to ground with a 0.01 F capacitor. Grounds for VCO Block. A 22 nF capacitor should be placed between this pin and VREG1 to reduce VCO noise.
34 35 36 37
DATA I/O DATA CLK CLKOUT MUXOUT
38 39 40 41 42 43 44 to 47 48
OSC2 OSC1 VDD3 VREG3 CPOUT VDD GND CVCO
Rev. A | Page 11 of 44
ADF7025 TYPICAL PERFORMANCE CHARACTERISTICS
CARRIER POWER 6.11dBm ATTEN 2.00dB MKR1 10.00KHz REF -60dBc/Hz 10.00dB/ -88.46dBc/Hz REF 10dBm PEAK 1 LOG 10dB/ ATTEN 20dB MKR4 3.482GHz SWEEP 16.52ms (601pts)
1
3
4
REF LEVEL 10.00dBm
05542-007
100Hz
FREQUENCY OFFSET
10Hz
START 100MHz RES BW 3MHz
VBW 3MHz
STOP 10.000GHz SWEEP 16.52ms (601pts)
Figure 6. Phase Noise Response at 915 MHz, VDD = 3.0 V, ICP = 0.867 mA
REF 10dBm NORM LOG 10dB/ ATTEN 20dB 1R 1 MKR1 400Hz 0.69dB
Figure 9. Harmonic Response, RFOUT Matched to 50 , No Filter
REF 15dBm NORM 1R LOG 10dB/ ATTEN 30dB Mkr1 1.834GHz -62.57dB
MARKER 1.834000000GHz -62.57dB LgAv W1S2 S3FC AA (f): FTun Swp
1
05542-008
CENTER 915.00MHz #RES BW 10kHz
VBW 10kHz
SPAN 5MHz SWEEP 60.32ms (601pts)
START 800MHz #RES BW 30kHz
VBW 30kHz
STOP 5.000GHz SWEEP 5.627s (601pts)
Figure 7. Output Spectrum in FSK Modulation (915 MHz, 172.8 kbps Data Rate, 200 kHz Frequency Deviation)
0 -5 -10
ATTENUATION LEVEL (dB)
Figure 10. Harmonic Response, Murata Dielectric Filter
20
600KHz FILTER B/W
15 10 11A
9A
-15 -20 -25 -30 -35 -40 -45
-1800 -1500 -1200 -900 -600 -300 0 300 600 900 1200 1500 1800
05542-009
450KHz FILTER B/W
PA OUTPUT POWER
5 0 7A -5 -10 -15
05542-053
5A
300KHz FILTER B/W
-20 -25
-50 FREQUENCY (KHz)
1
5
9
13 17 21 25 29 33 37 41 45 49 53 57 61 PA SETTING
Figure 8. Baseband Filter Response
Figure 11. PA Output Power vs. Setting
Rev. A | Page 12 of 44
05542-011
05542-010
ADF7025
20 0 -20
0 -1 -2 -3
RSSI READBACK LEVEL
DATA RATE = 384k, FDEV = 450k DATA RATE = 172k, FDEV = 200k DATA RATE = 38.4k, FDEV = 200k
ACTUAL INPUT LEVEL
RSSI LEVEL (dB)
LOG (BER)
-40 -60 -80
-4 -5 -6
-100 -120 -120
-100
-80
-60 -40 RF I/P (dB)
-20
0
20
05542-014
-8 -116
-108
-100 -90 RF I/P LEVEL (dBm)
-78
Figure 12. Digital RSSI Readback
70 60
Figure 15. BER vs. Data Rate (Combined Matching Network)
-50 -55 -60 = CORRELATOR = LINEAR
LEVEL OF REJECTION (dB)
SENSITIVITY POINT (dBm)
50 40 30 20 10
05542-013
-65 -70 -75 -80 -85 -90 -95 -100
0
05542-017
0
-10
-12
-6 0 6 12 OFFSET OF INTERFERER FROM WANTED SIGNAL (MHz)
50 100 150 200 250 300 350 400 450 500 550 600 650 700 750 800
DEVIATION FREQUENCY (kHz)
Figure 13. Wideband Interference Rejection; Wanted Signal (901 MHz, 38.4 kbps Data Rate, 200 kHz Frequency Deviation) at 6 dB Above Sensitivity Point; Interferer = CW Jammer
0 -1
Figure 16. Sensitivity vs. Mod Index (Data Rate = 384 kbps, Baseband Filter Bandwidth = 600 kHz), for Both Demodulator Types
-60 -65 -70 -75 -80 -85 -90 -95
05542-018
= CORRELATOR = LINEAR
SENSITIVITY POINT (dBm)
-2 -3
BER
BB BW = 450kHz BB BW = 600kHz
-4 -5 -6 -7 -8 -115 2.3V, +25C 3V, +25C 3.6V, +25C 2.3V, -40C 3V, -40C 3.6V, -40C 2.3V, +85C 3V, +85C 3.6V, +85C -110 -105 -100 -95 RF I/P LEVEL (dBm) -90
05542-015
-100 -105
-85
0
50
100 150 200 250 300 350 400 450 500 550 600 DEVIATION FREQUENCY (kHz)
Figure 14. Sensitivity vs. VDD and Temperature (172.8 kbps Data Rate, 200 kHz Frequency Deviation, Baseband Bandwidth 600 kHz)
Figure 17. Sensitivity vs. Mod Index (Data Rate = 172.8 kbps), for Both Demodulator Types
Rev. A | Page 13 of 44
05542-016
-7
ADF7025
-60 -65 -70
SENSITIVITY POINT (dBm)
= CORRELATOR = LINEAR
-75 -80 -85 -90 -95 -100 -105 -110 0 50
05542-052
BB BW = 300kHz
BB BW = 450kHz
BB BW = 600kHz
100 150 200 250 300 350 400 450 500 550 600 DEVIATION FREQUENCY (kHz)
Figure 18. Sensitivity vs. Mod Index (Data Rate = 38.4 kbps), for both Demodulator Types
Rev. A | Page 14 of 44
ADF7025 FREQUENCY SYNTHESIZER
REFERENCE INPUT SECTION
The on-board crystal oscillator circuitry (see Figure 19) can use an inexpensive quartz crystal as the PLL reference. The oscillator circuit is enabled by setting R1_DB12 high. It is enabled by default on power-up and is disabled by bringing CE low. Errors in the crystal can be corrected by adjusting the Fractional-N value (see the N Counter section). A single-ended reference (TCXO, CXO) can also be used. The CMOS levels should be applied to OSC2 with R1_DB12 set low. R Counter The 3-bit R counter divides the reference input frequency by an integer from 1 to 7. The divided-down signal is presented as the reference clock to the phase frequency detector (PFD). The divide ratio is set in Register 1. Maximizing the PFD frequency reduces the N value. This reduces the noise multiplied at a rate of 20 log(N) to the output, as well as reducing occurrences of spurious components. The R register defaults to R = 1 on power-up. PFD [Hz] = XTAL/R MUXOUT and Lock Detect
OSC1
CP2
OSC2
CP1
05542-019
The MUXOUT pin allows the user to access various digital points in the ADF7025. The state of MUXOUT is controlled by Bits R0_DB [29:31]. Regulator Ready Regulator ready is the default setting on MUXOUT after the transceiver has been powered up. The power-up time of the regulator is typically 50 s. Because the serial interface is powered from the regulator, the regulator must be at its nominal voltage before the ADF7025 can be programmed. The status of the regulator can be monitored at MUXOUT. When the regulator_ready signal on MUXOUT is high, programming of the ADF7025 can begin.
DVDD
Figure 19. Oscillator Circuit on the ADF7025
Two parallel resonant capacitors are required for oscillation at the correct frequency; their values are dependent on the crystal specification. They should be chosen so that the series value of capacitance added to the PCB track capacitance adds up to the load capacitance of the crystal, usually 20 pF. Track capacitance values vary from 2 pF to 5 pF, depending on board layout. Where possible, choose capacitors that have a very low temperature coefficient to ensure stable frequency operation over all conditions. CLKOUT Divider and Buffer The CLKOUT circuit takes the reference clock signal from the oscillator section, shown in Figure 19, and supplies a divideddown 50:50 mark-space signal to the CLKOUT pin. An even divide from 2 to 30 is available. This divide number is set in R1_DB [8:11]. On power-up, the CLKOUT defaults to divide-by-8.
DVDD CLKOUT ENABLE BIT
REGULATOR READY DIGITAL LOCK DETECT ANALOG LOCK DETECT R COUNTER OUTPUT N COUNTER OUTPUT PLL TEST MODES - TEST MODES MUX CONTROL MUXOUT
DGND
OSC1
05542-020
DIVIDER 1 TO 15
/2
CLKOUT
Figure 21. MUXOUT Circuit
Digital Lock Detect Digital lock detect is active high. The lock detect circuit is located at the PFD. When the phase error on five consecutive cycles is less than 15 ns, lock detect is set high. Lock detect remains high until a 25 ns phase error is detected at the PFD. Because no external components are needed for digital lock detect, it is more widely used than analog lock detect.
Figure 20. CLKOUT Stage
To disable CLKOUT, set the divide number to 0. The output buffer can drive up to a 20 pF load with a 10% rise time at 4.8 MHz. Faster edges can result in some spurious feedthrough to the output. A small series resistor (50 ) can be used to slow the clock edges to reduce these spurs at FCLK.
Rev. A | Page 15 of 44
05542-021
ADF7025
Analog Lock Detect This N-channel open-drain lock detect should be operated with an external pull-up resistor of 10 k nominal. When a lock has been detected, this output is high with narrow low-going pulses. Voltage Regulators The ADF7025 contains four regulators to supply stable voltages to the part. The nominal regulator voltage is 2.3 V. Each regulator should have a 100 nF capacitor connected between VREG and GND. When CE is high, the regulators and other associated circuitry are powered on, drawing a total supply current of 2 mA. Bringing the chip-enable pin low disables the regulators, reduces the supply current to less than 1 A, and erases all values held in the registers. The serial interface operates from a regulator supply; therefore, to write to the part, the user must have CE high and the regulator voltage must be stabilized. Regulator status (VREG4) can be monitored using the regulator ready signal from MUXOUT. Loop Filter The loop filter integrates the current pulses from the charge pump to form a voltage that tunes the output of the VCO to the desired frequency. It also attenuates spurious levels generated by the PLL. A typical loop filter design is shown in Figure 22.
REFERENCE IN 4R PFD/ CHARGE PUMP VCO
The fractional divide value gives very fine resolution at the output, where the output frequency of the PLL is calculated as
FOUT =
Fractional N XTAL x (Integer N + ) R 215
4N THIRD-ORDER - MODULATOR
05542-023
FRACTIONAL-N
INTEGER-N
Figure 23. Fractional-N PLL
The combination of the Integer-N (maximum = 255) and the Fractional-N (maximum = 16383/16384) gives a maximum N divider of 255 + 1. Therefore, the minimum usable PFD is PDFMIN [Hz] = Maximum Required Output Frequency/(255 + 1) For example, when operating in the European 868 MHz to 870 MHz band, PFDMIN equals 3.4 MHz. Voltage Controlled Oscillator
CHARGE PUMP OUT
VCO
05542-022
Figure 22. Typical Loop Filter Configuration
To minimize spurious emissions, the on-chip VCO operates from 1732 MHz to 1856 MHz. The VCO signal is then divided by 2 to give the required frequency for the transmitter and the required LO frequency for the receiver. The VCO should be re-centered, depending on the required frequency of operation, by programming the VCO adjust bits R1_DB [20:21]. For operation in the 862 MHz to 870 MHz band, it is recommended to use a VCO bias of at least Setting 10 and to set the VCO adjust bit to Setting 0. For operation in the 902 MHz to 928 MHz band, it is recommended to use a VCO bias of at least Setting 12 and to set the VCO adjust bit to Setting 3. This is to ensure correct operation under all conditions. The VCO is enabled as part of the PLL by the PLL-enable bit, R0_DB28. An additional frequency divide-by-2 is included to allow operation in the lower 431 MHz to 464 MHz bands. To enable operation in these bands, R1_DB13 should be set to 1. The VCO needs an external 22 nF between the VCO and the regulator to reduce internal noise.
In general, a loop filter bandwidth (LBW) of between the data rate and twice the data rate is recommended. Widening the LBW excessively reduces the time spent jumping between frequencies, but it can cause insufficient spurious attenuation. Narrow-loop bandwidths can result in the loop taking long periods of time to attain lock. For the ADF7025 in receive mode, the loop filter bandwidth affects the close-in blocking performance. The narrower the bandwidth of the loop filter, the greater the close-in interference resilience of the receiver. Careful design of the loop filter is critical to obtaining accurate FSK modulation. The free design tool ADIsimPLL can be used to design loop filters for the ADF7025.
N Counter
The feedback divider in the ADF7025 PLL consists of an 8-bit integer counter and a 14-bit - Fractional-N divider. The integer counter is the standard pulse-swallow type common in PLLs. This sets the minimum integer divide value to 31.
Rev. A | Page 16 of 44
ADF7025
VCO Bias Current VCO bias current can be adjusted using Bit R1_DB19 to Bit R1_DB16. To ensure VCO oscillation under all conditions, the minimum bias current setting is Setting 12 (0xC).
CHOOSING CHANNELS FOR BEST SYSTEM PERFORMANCE
The Fractional-N PLL allows the selection of any channel within 862 MHz to 928 MHz (and 431 MHz to 464 MHz using divide-by-2) to a resolution of <300 Hz. This also facilitates frequency-hopping systems. Careful selection of the RF transmit channels must be made to achieve best spurious performance. The architecture of Fractional-N results in some level of the nearest integer channel moving through the loop to the RF output. These beat-note spurs are not attenuated by the loop, if the desired RF channel and the nearest integer channel are separated by a frequency of less than the LBW. The occurrence of beat-note spurs is rare, because the integer frequencies are at multiples of the reference, which is typically >10 MHz. Beat-note spurs can be significantly reduced in amplitude by avoiding very small or very large values in the fractional register, using the frequency doubler. By having a channel 1 MHz away from an integer frequency, a 100 kHz loop filter can reduce the level to less than -45 dBc.
431 MHz to 464 MHz Operation
For operation in the 431 MHz to 464 MHz band, the frequency divide-by-2 has to be enabled. It is enabled by R1_DB13. Because this divide is external to the synthesizer loop, the feedback divider number (N + F) should be programmed to a value twice the desired RF output frequency.
VCO BIAS R1_DB (16:19) LOOP FILTER /2 MUX /2
TO PA AND N DIVIDER VCO
220F CVCO PIN
05542-024
VCO SELECT BIT
Figure 24. Voltage Controlled Oscillator
Rev. A | Page 17 of 44
ADF7025 TRANSMITTER
RF OUTPUT STAGE
The PA of the ADF7025 is based on a single-ended, controlled current, open-drain amplifier that has been designed to deliver up to 13 dBm into a 50 load at a maximum frequency of 928 MHz. The PA output current and, consequently, the output power are programmable over a wide range. The PA configuration is shown in Figure 25. The output power is independent of the state of the DATA I/O pin. The output power is set using Bits R2_DB [9:14].
R2_DB(30:31) 2 6
MODULATION SCHEME
Frequency Shift Keying (FSK) Frequency shift keying is implemented by setting the N value for the center frequency and then toggling this with the TxData line. The deviation from the center frequency is set using Bits R2_DB [15:23]. The deviation from the center frequency in Hz is
FSK DEVIATION [Hz] =
PFD x Modulation Number 214
where Modulation Number is a number from 1 to 511 (R2_DB(15:23)).
R2_DB(9:14)
IDAC
Select FSK using Bits R2_DB [6:8].
RFOUT +
R2_DB4 R2_DB5 DIGITAL LOCK DETECT
05542-025
4R
RFGND FROM VCO
PFD/ CHARGE PUMP
PA STAGE VCO
Figure 25. PA Configuration
FSK DEVIATION FREQUENCY /N -FDEV THIRD-ORDER - MODULATOR
05542-026
The PA is equipped with overvoltage protection, which makes it robust in severe mismatch conditions. Depending on the application, one can design a matching network for the PA to exhibit optimum efficiency at the desired radiated output power level for a wide range of different antennas, such as loop or monopole antennas. See the LNA/PA Matching section for details. PA Bias Currents Control Bits R2_DB [30:31] facilitate an adjustment of the PA bias current to further extend the output power control range, if necessary. If this feature is not required, the default value of 7 A is recommended. The output stage is powered down by resetting Bit R2_DB4.
+FDEV TxDATA
FRACTIONAL-N
INTEGER-N
Figure 26. FSK Implementation
Modulation Index
The choice of deviation frequency for a given data rate is critical to get optimum sensitivity performance from the ADF7025. The modulation index (MI) of an FSK modulated signal is defined as
MI =
2 x Frequency Deviation [Hz] Data Rate [bps]
It is recommended to use a MI > 1 for the ADF7025. The variation of receiver sensitivity with modulation index, for various data rates, can be observed in Figure 16, Figure 17, and Figure 18.
Rev. A | Page 18 of 44
ADF7025 RECEIVER
RF FRONT END
The ADF7025 is based on a fully integrated, zero-IF receiver architecture. The zero-IF architecture minimizes power consumption and the external component count while avoiding the need for image rejection. Figure 27 shows the structure of the receiver front end. The numerous programming options allow users to trade off sensitivity, linearity, and current consumption against each other in the way best suitable for their applications. To achieve a high level of resilience against spurious reception, the LNA features a differential input. Switch SW2 shorts the LNA input when transmit mode is selected (R0_DB27 = 0). This feature facilitates the design of a combined LNA/PA matching network, avoiding the need for an external Rx/Tx switch. See the LNA/PA Matching section for details on the design of the matching network.
I (TO FILTER) RFIN Tx/Rx SELECT [R0_DB27] RFINB LNA MODE [R6_DB15] LNA CURRENT [R6_DB(16:17)] LNA GAIN [R9_DB(20:21)] LNA/MIXER ENABLE [R8_DB6]
05542-027
Based on the specific sensitivity and linearity requirements of the application, it is recommended to adjust control bits LNA_mode (R6_DB15) and mixer_linearity (R6_DB18). The gain of the LNA is configured by the LNA_gain field, R9_DB [20:21] and can be set by either the user or the automatic gain control (AGC) logic.
Filter Settings/Calibration
Out-of-band interference is rejected by means of a fifth-order, low-pass filter (LPF). The bandwidth of the filter can be programmed to be 300 kHz, 450 kHz, or 600 kHz by means of Control Bits R1_DB [22:23] and should be chosen as a compromise between interference rejection and attenuation of the desired signal. A high-pass filter is also included as part of the low-pass filter to prevent against dc offset problems. The bandwidth of this filter is ~60 kHz. To avoid significant loss of FSK modulated signal in the filter, the frequency deviation needs to be significantly larger than this pole (refer to the Modulation Index section). The minimum allowable frequency deviation is 100 kHz. To compensate for manufacturing tolerances, the LPF should be calibrated once after power-up. The LPF calibration logic requires that the LPF divider in Bits R6_DB [20:28] be set depending on the crystal frequency. Once initiated by setting Bit R6_DB19, the calibration is performed automatically without any user intervention. The calibration time is 200 s, during which the ADF7025 should not be accessed. It is important not to initiate the calibration cycle before the crystal oscillator has fully settled. If the AGC loop is disabled, the gain of LPF can be set to three levels using the filter_gain field, R9_DB [20:21]. The filter gain is adjusted automatically, if the AGC loop is enabled.
SW2
LNA
LO Q (TO FILTER) MIXER LINEARITY [R6_DB18]
Figure 27. ADF7025 RF Front End
The LNA is followed by a quadrature downconversion mixer, which converts the RF signal direct to baseband. The output frequency of the synthesizer must be programmed to the value equal to the center frequency of the received channel. The LNA has two basic operating modes: high gain/low noise mode and low gain/low power mode. To switch between the two modes, use the LNA_mode bit, R6_DB15. The mixer is also configurable between a low current and an enhanced linearity mode using the mixer_linearity bit, R6_DB18.
Rev. A | Page 19 of 44
ADF7025
RSSI/AGC
The RSSI is implemented as a successive compression log amp following the baseband channel filtering. The log amp achieves 3 dB log linearity. It also doubles as a limiter to convert the signal-to-digital levels for the FSK demodulator. Offset correction is achieved using a switched capacitor integrator in feedback around the log amp. This uses the BB offset clock divide. The RSSI level is converted for user readback and digitally controlled AGC by an 80-level (7-bit) flash ADC. This level can be converted to input power in dBm.
OFFSET CORRECTION 1 A A A LATCH FSK DEMOD
RSSI Formula (Converting to dBm)
Input_Power [dBm] = -98 dBm + (Readback_Code + Gain_Mode_Correction ) x 0.5 where: Readback_Code is given by Bit RV7 to Bit RV1 in the readback register (see the Readback Format section). Gain_Mode_Correction is given by the values in Table 5. LNA gain and filter gain (LG2/LG1, FG2/FG1) are also obtained from the readback register. Table 5. Gain Mode Correction
LNA Gain (LG2, LG1) H (11) M (10) M (10) M (10) L (01) EL (00) Filter Gain (FG2, FG1) H (10) H (10) M (01) L (00) L (00) L (00) Gain Mode Correction 0 17 53 65 90 113
IFWR
IFWR
IFWR
IFWR
CLK ADC RSSI DEMOD
05542-028
R
Figure 28. RSSI Block Diagram
Offset Correction Clock
In Register 3, the user should set the BB offset clock divide bits R3_DB [4:5] to give an offset clock between 1 MHz and 2 MHz, where BBOS _CLK [Hz] = XTAL/(BBOS_CLK_DIVIDE). BBOS_CLK_DIVIDE can be set to 4, 8, or 16.
These numbers are for an unmodulated tone. For a modulated signal, the RSSI readback may have to be adjusted to get the required accuracy. An additional factor should also be introduced to account for losses in the front-end matching network/antenna.
AGC Information
In Register 9, the user should select automatic gain control by selecting Auto In R9_DB18 and Auto In R9_DB19. The user should then program AGC Low Threshold R9_DB [4:10] and AGC High Threshold R9_DB [11:17]. The default values for the low and high thresholds are 30 and 70, respectively; however, these are not the optimum settings for all operating conditions. The recommended values for the low and high thresholds are 15 and 79, respectively. In the AGC 2 register (Register 10), the user should program the AGC delay to be long enough to allow the loop to settle. The default/recommended value is 10.
FSK DEMODULATORS ON THE ADF7025
The two FSK demodulators on the ADF7025 are * FSK correlator/demodulator * Linear demodulator Select these using the Demod Select Bits R4_DB [4:5].
FSK CORRELATOR/DEMODULATOR
The quadrature outputs of the IF filter are first limited and then fed to a pair of digital frequency correlators that perform bandpass filtering of the binary FSK frequencies at (IF + FDEV) and (IF - FDEV). Data is recovered by comparing the output levels from each of the two correlators. The performance of this frequency discriminator approximates that of a matched filter detector, which is known to provide optimum detection in the presence of AWGN.
FREQUENCY CORRELATOR SLICER +
AGC _ Wait _ Time =
AGC _ DELAY x SEQ _ CLK _ DIVIDE XTAL
DB(4:13) DB(14)
DB(8:15)
Figure 29. FSK Correlator/Demodulator Block Diagram
Rev. A | Page 20 of 44
05542-029
Thus, in the worst case, if the AGC loop has to go through all five gain changes, AGC delay = 10, and SEQ_CLK = 200 kHz, then AGC settling = 10 x 5 s x 5 = 250 s. Minimum AGC_Wait_Time must be at least 25 s.
LIMITERS Q - FDEV + FDEV
POST DEMOD FILTER
I
DATA SYNCHRONIZER
AGC Settling = AGC_Wait_Time x Number of Gain Changes
0
Rx DATA
- 0
Rx CLK
ADF7025
Postdemodulator Filter
A second-order, digital low-pass filter removes excess noise from the demodulated bit stream at the output of the discriminator. The bandwidth of this postdemodulator filter is programmable and must be optimized for the user's data rate. If the bandwidth is set too narrow, performance is degraded due to intersymbol interference (ISI). If the bandwidth is set too wide, excess noise degrades the receiver's performance. Typically, the 3 dB bandwidth of this filter is set at approximately 0.75 times the user's data rate, using Bits R4_DB [6:15]. The discriminator BW is controlled in Register 6 by R6_DB [4:13] and is defined as Discriminator_BW = DEMOD_CLK/(4 x FDEV) where: DEMOD_CLK is as defined in the Register 3--Receiver Clock Register section. FDEV is the deviation from the carrier frequency in FSK modulation.
Bit Slicer
The received data is recovered by the threshold detecting the output of the postdemodulator low-pass filter. In the correlator/ demodulator, the binary output signal levels of the frequency discriminator are always centered on 0. Therefore, the slicer threshold level can be fixed at 0, and the demodulator performance is independent of the run-length constraints of the transmit data bit stream. This results in robust data recovery, which does not suffer from the classic baseline wander problems that exist in more traditional FSK demodulators.
Postdemodulator Bandwidth Register Settings
The 3 dB bandwidth of the postdemodulator filter is controlled by Bits R4_ DB [6:15] and is given by
Post _ Demod _ BW _ Setting = 210 x 2 x FCUTOFF DEMOD _ CLK
Data Synchronizer
An oversampled digital PLL is used to resynchronize the received bit stream to a local clock. The oversampled clock rate of the PLL (CDR_CLK) must be set at 32 times the data rate. See the Register 3--Receiver Clock Register section for a definition of how to program. The clock recovery PLL can accommodate frequency errors of up to 2%.
where FCUTOFF is the target 3 dB bandwidth in Hz of the postdemodulator filter. This should typically be set to 0.75 times the data rate (DR). Some sample settings for the FSK correlator/demodulator are DEMOD_CLK = 11.0592 MHz DR = 200 kbps FDEV = 300 kHz Therefore, FCUTOFF = 0.75 x 200 x 103 Hz Post_Demod_BW = 211 x x 150 x 103 Hz/(11.0592 MHz) Post_Demod_BW = Round (87.266) = 87 and Discriminator_BW = (11.0592 MHz )/(4 x 300 x 103) = 9.21 = 9 (rounded to the nearest integer) Table 6. Register Settings
Setting Name Post_Demod_BW Discriminator BW Register Address R4_DB [6:15] R6_DB [4:13] Value 0x09 0x58
FSK Correlator Register Settings
To enable the FSK correlator/demodulator, Bits R4_DB [5:4] should be set to 01. To achieve best performance, the bandwidth of the FSK correlator must be optimized for the specific deviation frequency that is used by the FSK transmitter.
Rev. A | Page 21 of 44
ADF7025
LINEAR FSK DEMODULATOR
A block diagram of the linear FSK demodulator is shown in Figure 30.
MUX 1 ADC RSSI OUTPUT LEVEL
AVERAGING FILTER
AUTOMATIC SYNC WORD RECOGNITION
The ADF7025 also supports automatic detection of the sync or ID fields. To activate this mode, the sync (or ID) word must be preprogrammed into the ADF7025. In receive mode, this preprogrammed word is compared to the received bit stream and, when a valid match is identified, the external pin INT/LOCK is asserted by the ADF7025. This feature can be used to alert the microprocessor that a valid channel has been detected. It relaxes the computational requirements of the microprocessor and reduces the overall power consumption. The INT/LOCK is automatically de-asserted again after nine data clock cycles. The automatic sync/ID word detection feature is enabled by selecting Demod Mode 2 or Demod Mode 3 in the demodulator setup register. Do this by setting R4_DB [25:23] = [010] or R4_DB [25:23] = [011]. Bits R5_DB [4:5] are used to set the length of the sync/ID word, which can be either 12 bits, 16 bits, 20 bits, or 24 bits long. The transmitter must transmit the MSB of the sync byte first and the LSB last to ensure proper alignment in the receiver sync byte detection hardware. For systems using FEC, an error tolerance parameter can also be programmed that accepts a valid match when up to three bits of the word are incorrect. The error tolerance value is assigned in R5_DB [6:7].
SLICER +
7 Rx DATA
I LIMITER Q
FREQ
DB(6:15)
Figure 30. Block Diagram of Linear FSK Demodulator
This method of frequency demodulation is useful when very short preamble length is required. A digital frequency discriminator provides an output signal that is linearly proportional to the frequency of the limiter outputs. The discriminator output is then filtered and averaged using a combined averaging filter and envelope detector. The demodulated FSK data is recovered by threshold-detecting the output of the averaging filter, as shown in Figure 30. In this mode, the slicer output shown in Figure 30 is routed to the data synchronizer PLL for clock synchronization. To enable the linear FSK demodulator, Bits R4_DB [4:5] are set to [00]. The 3 dB bandwidth of the postdemodulation filter is set in the same way as the FSK correlator/demodulator, which is set in R4_DB(6:15) and is defined as
Post _ Demod _ BW _ Setting = 210 x 2 x FCUTOFF DEMOD _ CLK
where: FCUTOFF is the target 3 dB bandwidth in Hz of the postdemodulator filter. DEMOD_CLK is as defined in the Register 3--Receiver Clock Register section.
Rev. A | Page 22 of 44
05542-030
0Hz LINEAR DISCRIMINATOR
ENVELOPE DETECTOR
-
ADF7025 APPLICATIONS SECTION
LNA/PA MATCHING
The ADF7025 exhibits optimum performance in terms of sensitivity, transmit power, and current consumption only if its RF input and output ports are properly matched to the antenna impedance. For cost-sensitive applications, the ADF7025 is equipped with an internal Rx/Tx switch, which facilitates the use of a simple combined passive PA/LNA matching network. Alternatively, an external Rx/Tx switch, such as the Analog Devices ADG919, can be used, which yields a slightly improved receiver sensitivity and lower transmitter power consumption. A first-order implementation of the matching network can be obtained by understanding the arrangement as two L-type matching networks in a back-to-back configuration. Due to the asymmetry of the network with respect to ground, a compromise between the input reflection coefficient and the maximum differential signal swing at the LNA input must be established. The use of appropriate CAD software is strongly recommended for this optimization. Depending on the antenna configuration, the user might need a harmonic filter at the PA output to satisfy the spurious emission requirement of the applicable government regulations. The harmonic filter can be implemented in various ways, such as a discrete LC filter or T-stage filter. Dielectric low-pass filter components such as the LFL18924MTC1A052 (for operation in the 915 MHz band), or LFL18869MTC2A160 (for operation in the 868 MHz band), both by Murata Mfg. Co., Ltd., represent an attractive alternative to discrete designs. The immunity of the ADF7025 to strong out-of-band interference can be improved by adding a band-pass filter in the Rx path.
External Rx/Tx Switch
Figure 31 shows a configuration using an external Rx/Tx switch. This configuration allows an independent optimization of the matching and filter network in the transmit and receive path, and is, therefore, more flexible and less difficult to design than the configuration using the internal Rx/Tx switch. The PA is biased through Inductor L1, while C1 blocks dc current. Both elements, L1 and C1, also form the matching network, which transforms the source impedance into the optimum PA load impedance, ZOPT_PA.
VBAT L1 OPTIONAL LPF ANTENNA CA LA ZOPT_PA ZIN_RFIN OPTIONAL BPF (SAW) RFIN LNA
Internal Rx/Tx Switch
Figure 32 shows the ADF7025 in a configuration where the internal Rx/Tx switch is used with a combined LNA/PA matching network. This is the configuration used in the ADF7025DB1 Evaluation Board. For most applications, the slight performance degradation of 1 dB to 2 dB caused by the internal Rx/Tx switch is acceptable, allowing the user to take advantage of the cost-saving potential of this solution. The design of the combined matching network must compensate for the reactance presented by the networks in the Tx and the Rx paths, taking the state of the Rx/Tx switch into consideration.
PA_OUT PA
RFINB
ADG919
Rx/Tx - SELECT CB
05542-031
ZIN_RFIN
ADF7025
VBAT C1 L1
Figure 31. ADF7025 with External Rx/Tx Switch
PA_OUT PA
CB
ADF7025
Due to the differential LNA input, the LNA matching network must be designed to provide both a single-ended to differential conversion and a complex conjugate impedance match. The network with the lowest component count that can satisfy these requirements is the configuration shown in Figure 31, which consists of two capacitors and one inductor.
Figure 32. ADF7025 with Internal Rx/Tx Switch
Rev. A | Page 23 of 44
05542-032
ZOPT_PA depends on various factors such as the required output power, the frequency range, the supply voltage range, and the temperature range. Selecting an appropriate ZOPT_PA helps to minimize the Tx current consumption in the application. This data sheet contains a number of ZOPT_PA values for representative conditions. Under certain conditions, however, it is recommended to obtain a suitable ZOPT_PA value by means of a load-pull measurement.
ANTENNA
OPTIONAL BPF OR LPF CA
ZOPT_PA ZIN_RFIN RFIN LA LNA
RFINB
ZIN_RFIN
ADF7025
The procedure typically requires several iterations until an acceptable compromise is reached. The successful implementation of a combined LNA/PA matching network for the ADF7025 is critically dependent on the availability of an accurate electrical model for the PC board. In this context, the use of a suitable CAD package is strongly recommended. To avoid this effort, however, a small form-factor reference design for the ADF7025 is provided, including matching and harmonic filter components. The design is on a 2-layer PCB to minimize cost. Gerber files are available on the www.analog.com website. Table 7. Minimum Register Writes Required for Tx/Rx Setup
Mode Tx Rx (FSK) Tx to Rx and Rx to Tx
1
Registers 0 1 0 1 0
2 2
4
6
91
Register 9 should be programmed in receive mode in order to set the recommended AGC threshold settings (low = 15, high = 79).
Figure 36 and Figure 37 show the recommended programming sequence and associated timing for power-up from standby mode.
TRANSMIT PROTOCOL AND CODING CONSIDERATIONS
PREAMBLE DATA FIELD CRC
05542-033
INTERFACING TO MICROCONTROLLER/DSP
Low level device drivers are available for interfacing to the ADF7025, the ADI ADuC84x microcontroller parts, or the Blackfin(R) BF53x DSPs using the hardware connections shown in Figure 34 and Figure 35.
ADuC84x MISO MOSI SCLOCK SS P3.7 P3.2/INT0 P2.4 GPIO P2.5 P2.6 P2.7 CE INT/LOCK SREAD SLE SDATA SCLK
05542-034
05542-035
SYNC WORD
ID FIELD
Figure 33. Typical Format of a Transmit Protocol
A dc-free preamble pattern is recommended for FSK demodulation. The recommended preamble pattern is a dc-free pattern such as a 10101010... pattern. Preamble patterns with longer run-length constraints such as 11001100.... can also be used. However, this results in a longer synchronization time of the received bit stream in the receiver. Manchester coding can be used for the entire transmit protocol. However, the remaining fields that follow the preamble header do not have to use dc-free coding. For these fields, the ADF7025 can accommodate coding schemes with a run-length of up to six bits without any performance degradation. If longer run-length coding must be supported, the ADF7025 has several other features that can be activated. These involve a range of programmable options that allow the envelope detector output to be frozen after preamble acquisition.
ADF7025
TxRxDATA RxCLK
Figure 34. ADuC84X to ADF7025 Connection Diagram
ADSP-BF533 SCK MOSI MISO PF5 RSCLK1 DT1PRI DR1PRI RFS1 PF6 VCC GND
ADF7025
SCLK SDATA SREAD SLE TxRxCLK TxRxDATA INT/LOCK CE VCC GND
DEVICE PROGRAMMING AFTER INITIAL POWER-UP
Table 7 lists the minimum number of writes needed to set up the ADF7025 in either Tx or Rx mode after CE is brought high. Additional registers can also be written to tailor the part to a particular application, such as setting up sync byte detection. When going from Tx to Rx or vice versa, the user needs to write only to the N register to alter the LO by 200 kHz and to toggle the Tx/Rx bit.
Figure 35. BF533 to ADF7025 Connection Diagram
Rev. A | Page 24 of 44
ADF7025
ADF7025 I DD
19mA TO 22mA 14mA
XTAL T0
3.65mA
2.0mA
REG. READY
WR0 WR1
VCO
WR3 WR4 WR6
AGC/ RSSI
CDR
T1
T2
T3
T4
T5
T6
T7 TON
T8
T9
RxDATA T11 TOFF
TIME
05542-036
Figure 36. Rx Programming Sequence and Timing Diagram
Table 8. Power-Up Sequence Description
Parameter T0 T1 T2, T3, T5, T6, T7 T4 Value 2 ms 10 s 32 x 1/SPI_CLK 1 ms Description/Notes XTAL starts power-up after CE is brought high. This typically depends on the XTAL type and the load capacitance specified. Time for regulator to power up. The serial interface can be written to after this time. Time to write to a single register. Maximum SPI_CLK is 25 MHz. The VCO can power-up in parallel with the XTAL. This depends on the CVCO capacitance value used. A value of 22 nF is recommended as a trade-off between phase noise performance and power-up time. This depends on the number of gain changes the AGC loop needs to cycle through and AGC settings programmed. This is described in more detail in the AGC Information section. This is the time for the clock and data recovery circuit to settle. This typically requires 5-bit transitions to acquire sync and is usually covered by the preamble. Number of bits in payload by the bit period. Signal to Monitor CLKOUT MUXOUT
CVCO pin
T8
150 s
Analog RSSI on TEST_A pin
T9 T11
5 x bit_period Packet length
Rev. A | Page 25 of 44
ADF7025
ADF7025 I DD
15mA TO 30mA
14mA
3.65mA
2.0mA
REG. READY WR0 WR1 T2 T3 T1
XTAL + VCO T4
WR2
T5 TON
TxDATA T12 TOFF
TIME
05542-037
Figure 37. Tx Programming Sequence and Timing Diagram
Rev. A | Page 26 of 44
ADF7025 SERIAL INTERFACE
The serial interface allows the user to program the eleven 32-bit registers using a 3-wire interface (SCLK, SDATA, and SLE). It consists of a level shifter, a 32-bit shift register, and 11 latches. Signals should be CMOS-compatible. The serial interface is powered by the regulator, and, therefore, is inactive when CE is low. Data is clocked into the register, MSB first, on the rising edge of each clock (SCLK). Data is transferred to one of 11 latches on the rising edge of SLE. The destination latch is determined by the value of the four control bits (C4 to C1). These are the bottom four LSBs, DB3 to DB0, as shown in the timing diagram in Figure 2. Data can also be read back on the SREAD pin.
Battery Voltage ADCIN/Temperature Sensor Readback
The battery voltage is measured at Pin VDD4. The readback information is contained in Bit RV1 to Bit RV7. This also applies for the readback of the voltage at the ADCIN pin and the temperature sensor. From the readback information, the battery or ADCIN voltage can be determined using VBATTERY = (Battery_Voltage_Readback)/21.1 VADCIN = (ADCIN_Voltage_Readback)/42.1
Silicon Revision Readback
The silicon revision readback word is valid without setting any other registers, especially directly after power-up. The silicon revision word is coded with four quartets in BCD format. The product code (PC) is coded with two quartets extending from Bit RV9 to Bit RV16. The revision code (RV) is coded with one quartet extending from Bit RV1 to Bit RV8. The product code should read back as PC = 0x25. The current revision code should read as RC = 0x08.
READBACK FORMAT
The readback operation is initiated by writing a valid control word to the readback register and setting the readback-enable bit (R7_DB8 = 1). The readback can begin after the control word has been latched with the SLE signal. SLE must be kept high while the data is being read out. Each active edge at the SCLK pin clocks the readback word out successively at the SREAD pin, as shown in Figure 38, starting with the MSB first. The data appearing at the first clock cycle following the latch operation must be ignored. RSSI Readback The RSSI readback operation yields valid results in Rx mode. The format of the readback word is shown in Figure 38. It comprises the RSSI level information (Bit RV1 to Bit RV7), the current filter gain (FG1 and FG2), and the current LNA gain (LG1 and LG2) setting. The filter and LNA gain are coded in accordance with the definitions in Register 9--AGC Register. The input power can be calculated from the RSSI readback value, as outlined in the RSSI/AGC section.
Filter Calibration Readback
The filter calibration readback word is contained in Bit RV1 to Bit RV8 and is for diagnostic purposes only. Using the automatic filter calibration function, accessible through Register 6, is recommended. Before filter calibration is initiated, Decimal 32 should be read back.
READBACK MODE DB15 DB14 DB13 DB12 DB11 DB10
READBACK VALUE DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
RSSI READBACK BATTERY VOLTAGE/ADCIN/ TEMP. SENSOR READBACK SILICON REVISION FILTER CAL READBACK
X
X
X
X
X
LG2
LG1
FG2
FG1
RV7
RV6
RV5
RV4
RV3
RV2
RV1
X RV16 0
X RV15 0
X RV14 0
X RV13 0
X RV12 0
X RV11 0
X RV10 0
X RV9 0
X RV8 RV8
RV7 RV7 RV7
RV6 RV6 RV6
RV5 RV5 RV5
RV4 RV4 RV4
RV3 RV3 RV3
RV2 RV2 RV2
RV1
05542-038
RV1 RV1
Figure 38. Readback Value Table
Rev. A | Page 27 of 44
ADF7025 REGISTERS
REGISTER 0--N REGISTER
PLL ENABLE Tx/Rx
MUXOUT 8-BIT INTEGER-N 15-BIT FRACTIONAL-N ADDRESS BITS
DB31
DB30
DB29
PLE1 DB28
DB27
DB26
DB25
DB24
DB23
DB22
DB21
DB20
DB19
DB18
DB17
DB16
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1 C2 (0)
C4 (0)
C3 (0)
TR1 0 1 0 1 M3 0 0 0 0 1 1 1 1 M2 0 0 1 1 0 0 1 1 M1 0 1 0 1 0 1 0 1
TRANSMIT/ RECEIVE TRANSMIT RECEIVE
M15 0 0 0 . . . 1 1 1 1
M14 0 0 0 . . . 1 1 1 1
M13 0 0 0 . . . 1 1 1 1
... ... ... ... ... ... ... ... ... ... ...
M3 0 0 0 . . . 1 1 1 1
M2 0 0 1 . . . 0 0 1 1
M1 0 1 0 . . . 0 1 0 1
FRACTIONAL DIVIDE RATIO 0 1 2 . . . 32764 32765 32766 32767
PLE1 PLL ENABLE PLL OFF PLL ON MUXOUT REGULATOR READY (DEFAULT) R DIVIDER OUTPUT N DIVIDER OUTPUT DIGITAL LOCK DETECT ANALOG LOCK DETECT THREE-STATE PLL TEST MODES - TEST MODES
N8 0 0 . . . 1 1 1
N7 0 0 . . . 1 1 1
N6 0 1 . . . 1 1 1
N5 1 0 . . . 1 1 1
N4 1 0 . . . 1 1 1
N3 1 0 . . . 1 1 1
N2 1 0 . . . 0 1 1
N1 1 0 . . . 1 0 1
N COUNTER DIVIDE RATIO 31 32 . . . 253 254 255
C1 (0)
05542-039
M15
M14
M13
M12
M10
TR1
M11
M3
M2
M1
M9
M8
M7
M6
M5
M4
M3
M2
Figure 39. Register 0--N Register
Register 0--N Register Comments
* The Tx/Rx bit (R0_DB27) configures the part in Tx or Rx mode and also controls the state of the internal Tx/Rx switch. * FOUT =
Fractional N XTAL x (Integer N + ) R 215
* If operating in 433 MHz band with the VCO band bit set, the desired frequency, FOUT, should be programmed to be twice the desired operating frequency, due to removal of the divide-by-2 stage in feedback path.
Rev. A | Page 28 of 44
M1
N8
N7
N6
N5
N4
N3
N2
N1
DB0
ADF7025
REGISTER 1--OSCILLATOR/FILTER REGISTER
IF FILTER BW VCO BAND CP CURRENT
VCO BIAS CLOCKOUT DIVIDE
XTAL DOUBLER
VCO ADJUST
XOSC ENABLE
R COUNTER
ADDRESS BITS
DB23
DB22
DB21
DB20
DB19
DB18
DB17
DB16
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1 C2 (0)
C4 (0)
C3 (0)
VA2 0 0 1 1
VA1 0 1 0 1
FREQUENCY OF OPERATION 850-920 860-930 870-940 880-950
X1 XTAL OSC 0 OFF 1 ON
V1 VCO BIAS CURRENT 0.25mA 0.5mA 4mA 0 1
VCO BAND (MHz) 862-956 431-478
R3 0 0 . . . 1
R2 0 1 . . . 1
R1 1 0 . . . 1
RF R COUNTER DIVIDE RATIO 1 2 . . . 7
VB4 0 0 . 1
VB3 0 0 . 1
VB2 0 1 . 1
VB1 1 0 . 1
D1 0 1
XTAL DOUBLER DISABLE ENABLED CLKOUT DIVIDE RATIO OFF 2 4 . . . 30
IR2 IR1 0 0 1 1 0 1 0 1
FILTER BANDWIDTH 600kHz 900kHz 1200kHz NOT USED
CP2 0 0 1 1
Figure 40. Register 1--Oscillator/Filter Register
Register 1--Oscillator/Filter Register Comments
* The VCO Adjust Bits R1_DB[20:21] should be set to 0 for operation in the 862 MHz to 870 MHz band and set to 3 for operation in the 902 MHz to 928 MHz band. * VCO bias setting should be 0xA for operation in the 862 MHz to 870 MHz band and 0xC for operation in the 902 MHz to 928 MHz band. All VCO gain numbers are specified for these settings.
Rev. A | Page 29 of 44
05542-040
CP1 RSET 0 1 0 1
ICP(MA) 3.6k 0.3 0.9 1.5 2.1
CL4 0 0 0 . . . 1
CL3 0 0 0 . . . 1
CL2 0 0 1 . . . 1
CL1 0 1 0 . . . 1
C1 (1)
DD2
DD1
VB4
VB3
VB2
VB1
CL4
CL3
CL2
CL1
VA2
VA1
IR2
IR1
D1
R3
R2
R1
V1
X1
DB0
ADF7025
REGISTER 2--TRANSMIT MODULATION REGISTER
MUTE PA UNTIL LOCK PA ENABLE INDEX COUNTER TxDATA INVERT
PA BIAS GFSK MOD CONTROL MODULATION PARAMETER POWER AMPLIFIER MODULATION SCHEME ADDRESS BITS
DB31
DB30
DB29
DB28
DB27
DB26
DB25
DB24
DB23
DB22
DB21
DB20
DB19
DB18
DB17
DB16
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1 C2 (1)
C4 (0)
C3 (0)
PE1 IC2 IC1 MC3 MC2 MC1 X X X X X 0 1
POWER AMPLIFIER OFF ON
DI1 0 1 TxDATA TxDATA
FOR FSK MODE, D2 .... D3 D9 0 0 0 0 . 1 .... .... .... .... .... .... 0 0 0 0 . 1 0 0 1 1 . 1
D1 0 1 0 1 . 1
F DEVIATION PLL MODE 1 x FSTEP 2 x FSTEP 3 x FSTEP . 511 x FSTEP
MUTE PA UNTIL MP1 LOCK DETECT HIGH 0 1 OFF ON
PA2 0 0 1 1
PA1 0 1 0 1
PA BIAS 5A 7A 9A 11A
S3 S2 S1 0
0
MODULATION SCHEME FSK INVALID
0
XXX
POWER AMPLIFIER OUTPUT LEVEL P1 P2 . . P6 0 0 0 0 . . 1 . . . . . . 1 . . . . . . . X 0 0 1 . . 1 X 0 1 0 . . 1 PA OFF -16.0dBm -16 + 0.45dBm -16 + 0.90dBm . . 13dBm
C1 (0)
05542-041
MC3
MC2
MC1
MP1
Figure 41. Register 2--Transmit Modulation Register
Register 2--Transmit Modulation Register Comments
* FSTEP = PFD/1214. * When operating in the 431 MHz to 464 MHz band, FSTEP = PFD/1215. * PA bias default = 9 A.
Rev. A | Page 30 of 44
PE1
PA2
PA1
DI1
IC2
IC1
D9
D8
D7
D6
D5
D4
D3
D2
D1
P6
P5
P4
P3
P2
P1
S3
S2
S1
DB0
ADF7025
REGISTER 3--RECEIVER CLOCK REGISTER
DEMOD CLOCK DIVIDE BB OFFSET CLOCK DIVIDE
ADDRESS BITS
SEQUENCER CLOCK DIVIDE
CDR CLOCK DIVIDE
DB23
DB22
DB21
DB20
DB19
DB18
DB17
DB16
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1 C2(1)
C4(0)
C3(0)
SK8 0 0 . 1 1
SK7 0 0 . 1 1
... ... ... ... ... ...
SK3 0 0 . 1 1
SK2 0 1 . 1 1
SK1 1 0 . 0 1
SEQ_CLK_DIVIDE 1 2 . 254 255
BK2 0 0 1 OK2 0 0 1 1 OK1 0 1 0 1
BK1 0 1 x
BBOS_CLK_DIVIDE 4 8 16
DEMOD_CLK_DIVIDE 4 1 2 3
FS8 0 0 . 1 1
FS7 0 0 . 1 1
... ... ... ... ... ...
FS3 0 0 . 1 1
FS2 0 1 . 1 1
FS1 1 0 . 0 1
CDR_CLK_DIVIDE 1 2 . 254 255
C1(1)
05542-042
OK2
OK1
BK2
Figure 42. Register 3--Receiver Clock Register
Register 3--Receiver Clock Register Comments
* Baseband offset clock frequency (BBOS_CLK) must be greater than 1 MHz and less than 2 MHz, where: XTAL BBOS _ CLK = BBOS _ CLK _ DIVIDE * The demodulator clock (DEMOD_CLK) must be < 12 MHz, where: XTAL DEMOD _ CLK = DEMOD _ CLK _ DIVIDE * Data/clock recovery frequency (CDR_CLK) should be within 2% of (32 x data rate), where: DEMOD _ CLK CDR _ CLK = CDR _ CLK _ DIVIDE Note that this can affect the choice of XTAL, depending on the desired data rate. * The sequencer clock (SEQ_CLK) supplies the clock to the digital receive block. It should be close to 100 kHz. XTAL SEQ _ CLK = SEQ _ CLK _ DIVIDE
Rev. A | Page 31 of 44
BK1
SK8
SK7
SK6
SK5
SK4
SK3
SK2
SK1
FS8
FS7
FS6
FS5
FS4
FS3
FS2
FS1
DB0
ADF7025
REGISTER 4--DEMODULATOR SETUP REGISTER
DEMOD LOCK/ DB24 SYNC WORD MATCH DEMOD SELECT
DEMODULATOR LOCK SETTING
POSTDEMODULATOR BW
ADDRESS BITS
DB31
DB30
DB29
DB28
DB27
DB26
DB25
DB23
DB22
DB21
DB20
DB19
DB18
DB17
DB16
DW10 DB15
DW9 DB14
DW8 DB13
DW7 DB12
DB11
DW5 DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1 C2(0)
C4(0)
C3(1)
DS2 0 0 1 1 DEMOD MODE LM2 LM1 DL8 0 1 2 3 4 5 0 0 0 0 1 1 0 0 1 1 0 1 0 1 0 1 X DL8 DEMOD LOCK/SYNC WORD MATCH SERIAL PORT CONTROL - FREE RUNNING SERIAL PORT CONTROL - LOCK THRESHOLD SYNC WORD DETECT - FREE RUNNING SYNC WORD DETECT - LOCK THRESHOLD INTERRUPT/LOCK PIN LOCKS THRESHOLD DEMOD LOCKED AFTER DL8-DL1 BITS INT/LOCK PIN - - OUTPUT OUTPUT INPUT -
DS1 0 1 0 1
DEMODULATOR TYPE LINEAR DEMODULATOR CORRELATOR/DEMODULATOR INVALID INVALID
MODE5 ONLY DL8 0 0 0 . 1 1 DL7 0 0 0 . 1 1 ... ... ... ... ... ... ... DL3 0 0 0 . 1 1 DL2 0 0 1 . 1 1 DL1 0 1 0 . 0 1 LOCK_THRESHOLD_TIMEOUT 0 1 2 . 254 255
C1(0)
05542-043
DW6
DW4
DW3
DW2
DW1
LM2
LM1
DS2
Figure 43. Register 4--Demodulator Setup Register
Register 4--Demodulator Setup Register Comments
* Demodulator Mode 1, Demodulator Mode 3, Demodulator Mode 4, and Demodulator Mode 5 are modes that can be activated to allow the ADF7025 to demodulate data-encoding schemes that have run-length constraints greater than 7. * Post_Demod_BW = the data rate. * For Mode 5, the Timeout Delay to Lock Threshold = (LOCK_THRESHOLD_SETTING)/SEQ_CLK, where SEQ_CLK is defined in the Register 3--Receiver Clock Register section.
2 11 x x FCUTOFF , where the cutoff frequency (FCUTOFF) of the postdemodulator filter should typically be 0.75 times DEMOD_CLK
Rev. A | Page 32 of 44
DS1
DL8
DL7
DL6
DL5
DL4
DL3
DL2
DL1
DB0
ADF7025
REGISTER 5--SYNC BYTE REGISTER
MATCHING TOLERANCE SYNC BYTE LENGTH
SYNC BYTE SEQUENCE CONTROL BITS
DB31
DB30
DB29
DB28
DB27
DB26
DB25
DB24
DB23
DB22
DB21
DB20
DB19
DB18
DB17
DB16
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1 C2(0)
C4(0)
C3(1)
PL2 0 0 1 1
PL1 0 1 0 1
SYNC BYTE LENGTH 12 BITS 16 BITS 20 BITS 24 BITS
MATCHING MT2 MT1 TOLERANCE
05542-044
0 0 1 1
0 1 0 1
0 ERRORS 1 ERROR 2 ERRORS 3 ERRORS
Figure 44. Register 5--Sync Byte Register
Register 5--Sync Byte Register Comments
* Sync byte detect is enabled by programming Bits R4_DB [25:23] to 010 or 011. * This register allows a 24-bit sync byte sequence to be stored internally. If the sync byte detect mode is selected, then the INT/LOCK pin goes high when the sync byte has been detected in Rx mode. Once the sync word detect signal has gone high, it goes low again after nine data bits. * The transmitter must transmit the MSB of the sync byte first and the LSB last to ensure proper alignment in the receiver sync byte detection hardware. * Choose a sync byte pattern that has good autocorrelation properties.
Rev. A | Page 33 of 44
C1(1)
MT2
MT1
PL2
PL1
DB0
ADF7025
REGISTER 6--CORRELATOR/DEMODULATOR REGISTER
LNA MODE IF FILTER CAL MIXER LINEARITY Rx RESET DOT PRODUCT LNA CURRENT RxDATA INVERT IF FILTER DIVIDER DISCRIMINATOR BW ADDRESS BITS
DB31
DB30
DB29
DB28
DB27
DB26
DB25
DB24
DB23
DB22
DB21
DB20
DB19
DB18
DB17
DB16
DB15
DB14
TD10 DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1 C2(1)
C4(0)
C3(1)
DEMOD RESET CDR RESET RxDATA INVERT RxDATA RxDATA
CA1 FILTER CAL 0 1 NO CAL CALIBRATE
DP1 0 1
DOT PRODUCT CROSS PRODUCT INVALID
ML1 MIXER LINEARITY 0 1 DEFAULT HIGH LI2 0 LI1 0 LNA BIAS 800A (DEFAULT)
LG1 LNA MODE 0 1 DEFAULT REDUCED GAIN
RI1 0 1
FC9 0 0 . . . . 1
. . . . . . . .
FC6 0 0 . . . . 1
FC5 0 0 . . . . 1
FC4 0 0 . . . . 1
FC3 0 0 . . . . 1
FC2 0 1 . . . . 1
FC1 1 0 . . . . 1
FILTER CLOCK DIVIDE RATIO 1 2 . . . . 511
C1(0)
05542-045
ML1
CA1
LG1
DP1
FC9
FC8
FC7
FC6
FC5
FC4
FC3
FC2
FC1
TD9
TD8
TD7
TD6
TD5
TD4
TD3
TD2
Figure 45. Register 6--Correlator/Demodulator Register
Register 6--Correlator/Demodulator Register Comments
* See the FSK Correlator/Demodulator section for an example of how to determine register settings. * Nonadherence to correlator programming guidelines results in poor sensitivity. * The filter clock is used to calibrate the LP filter. The filter clock divide ratio should be adjusted so that the frequency is 50 kHz. The formula is XTAL/FILTER_CLOCK_DIVIDE. * The filter should be calibrated only when the crystal oscillator is settled. The filter calibration is initiated every time Bit R6_DB19 is set high. * Discriminator_BW = DEMOD_CLK/(4 x DEVIATION_Frequency). See the FSK Correlator/Demodulator section. Maximum value = 600. * When LNA Mode = 1 (reduced gain mode), the Rx is prevented from selecting the highest LNA gain setting. This can be used when linearity is a concern. See the Readback Format section for details of the different Rx modes.
Rev. A | Page 34 of 44
TD1
RI1
LI2
LI1
DB0
ADF7025
REGISTER 7--READBACK SETUP REGISTER
READBACK SELECT DB8 RB3 DB7 RB2 DB6 RB1 ADC MODE DB5 AD2 DB4 AD1 DB3 C4(0) CONTROL BITS DB2 C3(1) DB1 C2(1) DB0 C1(1)
RB3 0 1
READBACK DISABLED ENABLED RB2 0 0 1 1 RB1 0 1 0 1 READBACK MODE INVALID ADC OUTPUT FILTER CAL SILICON REV
AD2 0 0 1 1
AD1 0 1 0 1
ADC MODE MEASURE RSSI BATTERY VOLTAGE TEMP SENSOR TO EXTERNAL PIN
Figure 46. Register 7--Readback Setup Register
Register 7--Readback Setup Register Comments
* Readback of the measured RSSI value is valid only in Rx mode. Readback of the battery voltage, the temperature sensor, and the voltage at the external pin is not available in Rx mode if AGC is enabled. * Readback of the ADC value is valid in Tx mode only if the log amp/RSSI has not been disabled through the Power-Down Bit R8_DB10. The log amp/RSSI section is active by default upon enabling Tx mode. * See the Readback Format section for more information.
Rev. A | Page 35 of 44
05542-046
ADF7025
REGISTER 8--POWER-DOWN TEST REGISTER
INTERNAL Tx/Rx SWITCH ENABLE PA ENABLE Rx MODE LNA/MIXER ENABLE DEMOD ENABLE ADC ENABLE FILTER ENABLE VCO ENABLE LOG AMP/ RSSI SYNTH ENABLE CONTROL BITS
DB15
DB14
DB13 PD7
DB12 SW1
DB11 LR2
DB10 LR1
DB9 PD6
DB8 PD5
DB7 PD4
DB6 PD3
DB5 PD2
DB4 PD1
DB3 C4(1)
DB2 C3(0)
DB1 C2(0)
DB0 C1(0)
PD7 0 1
PA (Rx MODE) PA OFF PA ON SW1 Tx/Rx SWITCH 0 1 DEFAULT (ON) OFF LR2 X X LR1 0 1 RSSI MODE RSSI OFF RSSI ON PD6 0 1 DEMOD ENABLE DEMOD OFF DEMOD ON PD5 0 1 PD4 0 1 ADC ENABLE ADC OFF ADC ON PD3 0 1
PLE1 (FROM REG 0) 0 0 0 0 1
PD2 0 0 1 1 X
PD1 0 1 0 1 X
LOOP CONDITION VCO/PLL OFF PLL ON VCO ON PLL/VCO ON PLL/VCO ON
LNA/MIXER ENABLE LNA/MIXER OFF LNA/MIXER ON
FILTER ENABLE FILTER OFF FILTER ON
Figure 47. Register 8--Power-Down Test Register
Register 8--Power-Down Test Register Comments
* For a combined LNA/PA matching network, Bit R8_DB12 should always be set to 0. This is the power-up default condition. * It is not necessary to write to this register under normal operating conditions.
Rev. A | Page 36 of 44
05542-047
ADF7025
REGISTER 9--AGC REGISTER
DIGITAL TEST IQ FILTER GAIN LNA GAIN
GAIN CONTROL AGC SEARCH
FILTER CURRENT
AGC HIGH THRESHOLD
AGC LOW THRESHOLD
ADDRESS BITS
DB31
DB30
DB29
DB28
DB27
DB26
DB25
DB24
DB23
DB22
DB21
DB20
DB19
DB18
DB17
DB16
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1 C2(0)
C4(1)
C3(0)
FI1 0 1
FILTER CURRENT LOW HIGH FG2 0 0 1 1 FG1 0 1 0 1 FILTER GAIN 8 24 72 INVALID
GS1 AGC SEARCH 0 1 AUTO AGC HOLD SETTING GL7 0 0 0 0 . . . 1 1 1 GL6 0 0 0 0 . . . 1 1 1 GL5 0 0 0 0 . . . 1 1 1 GL4 0 0 0 0 . . . 1 1 1 GL3 0 0 0 1 . . . 1 1 1 GL2 0 1 1 0 . . . 0 1 1 GL1 1 0 1 0 . . . 1 0 1
AGC LOW THRESHOLD 1 2 3 4 . . . 61 62 63
GC1 GAIN CONTROL 0 1 AUTO USER
RSSI LEVEL GH7 GH6 GH5 GH4 GH3 GH2 GH1 CODE 0 0 0 0 . . . 1 1 1 0 0 0 0 . . . 0 0 0 0 0 0 0 . . . 0 0 1 0 0 0 0 . . . 1 1 0 0 0 0 1 . . . 1 1 0 0 1 1 0 . . . 1 1 0 1 0 1 0 . . . 0 1 0 1 2 3 4 . . . 78 79 80
LG2 0 0 1 1
LG1 0 1 0 1
LNA GAIN <1 3 10 30
C1(1)
05542-048
GC1
GH7
GH6
GH5
GH4
GH3
GH2
GH1
GS1
FG2
FG1
LG2
LG1
GL7
GL6
GL5
GL4
GL3
GL2
Figure 48. Register 9--AGC Register
Register 9--AGC Register Comments
* The recommended AGC threshold settings are AGC_LOW_THRESHOLD = 15, AGC_HIGH_THRESHOLD = 79. The default settings (that is, if this register is not programmed) are AGC_LOW_THRESHOLD = 30, default AGC_HIGH_THRESHOLD = 70. See the RSSI/AGC section for details. * AGC high and low settings must be more than 30 apart to ensure correct operation. * LNA gain of 30 is available only if LNA mode, R6_DB15, is set to 0.
Rev. A | Page 37 of 44
GL1
FI1
DB0
ADF7025
REGISTER 10--AGC 2 REGISTER
RESERVED UP/DOWN SELECT I/Q SELECT I/Q
I/Q PHASE ADJUST I/Q GAIN ADJUST AGC DELAY LEAK FACTOR PEAK RESPONSE ADDRESS BITS
DB31
DB30
DB29
SIQ2 DB28
DB27
DB26
DB25
DB24
DB23
SIQ1 DB22
DB21
DB20
DB19
DB18
DB17
DB16
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1 C2(1)
C4(1)
C3(0)
SIQ2 SELECT IQ 0 1 PHASE TO I CHANNEL PHASE TO Q CHANNEL
SIQ2 SELECT IQ 0 1 GAIN TO I CHANNEL GAIN TO Q CHANNEL
DEFAULT = 0xA DEFAULT = 0xA DEFAULT = 0x2
05542-049
Figure 49. Register 10--AGC 2 Register
Register 10--AGC 2 Register Comments
* Register 10 is not used under normal operating conditions. * If adjusting AGC Delay or Leak Factor, clear Bit DB31 to Bit DB16.
Rev. A | Page 38 of 44
C1(0)
GC5
GC4
GC3
GC2
GC1
GL7
GL6
GL5
UD1
DH4
DH3
DH2
DH1
GL4
PH4
PH3
PH2
PH1
PR4
PR3
PR2
PR1
R1
DB0
ADF7025
REGISTER 12--TEST REGISTER
DB31 PRESCALER OSC TEST
ANALOG TEST MUX IMAGE FILTER ADJUST DIGITAL TEST MODES
COUNTER RESET
SOURCE
FORCE LD HIGH
- TEST MODES
PLL TEST MODES
ADDRESS BITS
DB30
DB29
DB28
DB27
DB26
DB25
DB24
DB23
DB22
DB21
DB20
DB19
DB18
DB17
DB16
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1 C2(0)
C4(1)
C3(1)
P 0 1
PRESCALER 4/5 (DEFAULT) 8/9 CS1 0 1 CAL SOURCE INTERNAL SERIAL IF BW CAL
DEFAULT = 32. INCREASE NUMBER TO INCREASE BW IF USER CAL ON
CR1 COUNTER RESET 0 1 DEFAULT RESET
C1(0)
05542-050
PRE
QT1
CS1
SF6
SF5
SF4
SF3
SF2
SF1
T9
T8
T7
T6
T5
T4
T3
T2
Figure 50. Register 12--Test Register
Using the Test DAC on the ADF7025 to Implement Analog FM DEMOD and Measuring SNR
The test DAC allows the output of the postdemodulator filter for both the linear and correlator/demodulators to be viewed externally. It takes the 16-bit filter output and converts it to a high frequency, single-bit output using a second-order error feedback - converter. The output can be viewed on the XCLKOUT pin. This signal, when IF-filtered appropriately, can then be used to * Monitor the signals at the FSK postdemodulator filter output. This allows the demodulator output SNR to be measured. Eye diagrams can also be constructed of the received bit stream to measure the received signal quality. * Provide analog FM demodulation. While the correlators and filters are clocked by DEMOD_CLK, CDR_CLK clocks the test DAC. Note that, although the test DAC functions in a regular user mode, the best performance is achieved when the CDR_CLK is increased up to or above the frequency of DEMOD_CLK. The CDR block does not function when this condition exists.
Programming the test register, Register 12, enables the test DAC. Both the linear and correlator/demodulator outputs can be multiplexed into the DAC. Register 13 allows a fixed offset term to be removed from the signal in the case where there is an error in the received signal frequency. If there is a frequency error in the signal, the user should program half this value into the offset removal field. It also has a signal gain term to allow usage of the maximum dynamic range of the DAC.
Setting Up the Test DAC
* * Digital test modes = 7: enables the test DAC, with no offset removal (0x0001C00C). Digital test modes = 10: enables the test DAC, with offset removal.
The output of the active demodulator drives the DAC; that is, if the FSK correlator/demodulator is selected, the correlator filter output drives the DAC.
Rev. A | Page 39 of 44
T1
DB0
ADF7025
REGISTER 13--OFFSET REMOVAL AND SIGNAL GAIN REGISTER
TEST DAC GAIN TEST DAC OFFSET REMOVAL PULSE EXTENSION KI KP CONTROL BITS
DB31
DB30
DB29
DB28
DB27
DB26
DB25
DB24
DB23
DB22
DB21
DB20
DB19
DB18
DB17
DB16
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1 C2(0)
C4(1)
C3(1)
PE4 0 0 0 . . . 1
PE3 0 0 0 . . . 1
PE2 0 0 1 . . . 1
PE1 0 1 0 . . . 1
PULSE EXTENSION NORMAL PULSE WIDTH 2x PULSE WIDTH 3x PULSE WIDTH . . . 16x PULSE WIDTH
C1(1)
05542-051
PE4
PE3
PE2
Figure 51. Register 13--Offset Removal and Signal Gain Register
Register 13--Offset Removal and Signal Gain Register Comments
Because the linear demodulator output is proportional to frequency, it usually consists of an offset combined with a relatively low signal. The offset can be removed, up to a maximum of 1.0, and gained to use the full dynamic range of the DAC, as follows: DAC_Input = (2^ Test_DAC_Gain) x (Signal - Test_DAC_Offset_Removal/4096).
Rev. A | Page 40 of 44
PE1
DB0
ADF7025 OUTLINE DIMENSIONS
7.00 BSC SQ 0.60 MAX 0.60 MAX
37 36
0.30 0.23 0.18
48 1
PIN 1 INDICATOR
PIN 1 INDICATOR
TOP VIEW
6.75 BSC SQ
EXPOSED PAD
(BOTTOM VIEW)
4.25 4.10 SQ 3.95
0.50 0.40 0.30
25 24
12 13
0.25 MIN 5.50 REF
1.00 0.85 0.80
12 MAX
0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM 0.50 BSC
SEATING PLANE
0.20 REF
COPLANARITY 0.08
COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2
Figure 52. 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 7 mm x 7 mm Body, Very Thin Quad (CP-48-3) Dimensions shown in millimeters
ORDERING GUIDE
Model ADF7025BCPZ1 ADF7025BCPZ-RL1 ADF7025BCPZ-RL71 EVAL-ADF70XXMB EVAL-ADF70XXMB2 EVAL-ADF7025DB1
1
Temperature Range -40C to +85C -40C to +85C -40C to +85C
Package Description 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ] Control Mother Board Evaluation Platform 902-928 MHz Daughter Board
Package Option CP-48-3 CP-48-3 CP-48-3
Z = Pb-free part.
Rev. A | Page 41 of 44
ADF7025 NOTES
Rev. A | Page 42 of 44
ADF7025 NOTES
Rev. A | Page 43 of 44
ADF7025 NOTES
(c)2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05542-0-2/06(A)
Rev. A | Page 44 of 44

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